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PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT
ClockWorksTM SY10E196 SY100E196
FEATURES
s Up to 2ns delay range s Extended 100E VEE range of -4.2V to -5.5V s s s s s s s
DESCRIPTION
The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjustment organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.
20ps digital step resolution
Linear input for tighter resolution >1GHz bandwidth On-chip cascade circuitry 75Kk input pulldown resistor Fully compatible with Motorola MC10E/100E196 Available in 28-pin PLCC package
PIN CONFIGURATION
NC
18 17
25 24 23 22 21 20 19
D1 D0 LEN VEE IN IN VBB
26 27 28 1 2 3 4 5 6 7 8 9 10 11
D6 D7
D2 D3
D4 D5
TOP VIEW PLCC J28-1
16 15 14 13 12
FTUNE NC VCC VCCO Q Q VCCO
PIN NAMES
Pin IN/IN Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Minimum Delay Set Maximum Delay Set Cascade Signal Linear Voltage Input VCC to Output
EN SET MIN SET MAX
NC NC
CASCADE
CASCADE
EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE FTUNE VCCO
Rev.: E
Amendment: /0
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Issue Date: October, 1998
ClockWorksTM SY10E196 SY100E196
VBB IN IN 1 1 1 1 1 1 EN *1.25 *1.5 LEN Latch 7-Bit Latch D Q LEN SET MIN SET MAX 1 1 0 0 1 0 0 0 4 gates 1 0 8 gates 1 0 16 gates 1
FTUNE
0
Q
1
1
Q
Cascade
Linear Ramp
CASCADE
CASCADE D0 D1 D2 D3 D4 D5 D6 D7
*Delays are 25% or 50% longer than standard (standard = 80ps).
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BLOCK DIAGRAM
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ClockWorksTM SY10E196 SY100E196
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 130 130 156 156 -- -- 130 130 156 156 -- -- 130 150 156 179 Min. -- Typ. -- Max. 150 -- TA = +25C Min. Typ. -- Max. 150 -- TA = +85C Min. Typ. -- Max. 150 Unit A mA Condition -- --
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ClockWorksTM SY10E196 SY100E196
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output IN to Q; Tap = 0 IN to Q; Tap = 127 EN to Q; Tap = 0 D7 to CASCADE Programmable Range tPD (max.) - tPD (min.) Step Delay D0 High D1 High D2 High D3 High D4 High D5 High D6 High Linearity Duty Cycle Skew, tPHL-tPLH Set-up Time D to LEN D to IN EN to IN Hold Time LEN to D IN to EN Release Time EN to IN SET MAX to LEN SET MIN to LEN Jitter Rise/Fall Times 20-80% (Q) 20-80% (CASCADE) Min. 1210 3320 1250 300 2000 Typ. 1360 3570 1450 450 2175 Max. 1510 3820 1650 700 -- Min. 1240 3380 1275 300 2050 TA = +25C Typ. 1390 3630 1475 450 2240 Max. 1540 3880 1675 700 -- TA = +85C Min. 1440 3920 1350 300 2375 Typ. 1590 4270 1650 450 2580 Max. 1765 4720 1950 700 -- ps ps -- -- 55 115 250 505 1000 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 17 34 68 136 272 544 1088 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 105 180 325 620 1190 -- -- -- -- -- -- -- -- -- -- -- 325 650 -- -- 55 115 250 515 1030 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 17.5 35 70 140 280 560 1120 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 105 180 325 620 1220 -- -- -- -- -- -- -- -- -- -- -- 325 650 -- -- 65 140 305 620 1240 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 21 42 84 168 336 672 1344 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 120 205 380 740 1450 -- -- -- -- -- ps -- -- ps -- -- -- -- 325 650 ps ps 5 4 -- ps ps 2 3 7 1 -- 6 Unit ps Condition --
tRANGE t
Lin tskew tS
tH
tR
tjit tr tf
8 --
NOTES: 1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 2. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set. 3. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75mV to that IN/IN transition. 4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75mV to that IN/IN transition. 5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). Typically, the device will be monotonic to the D0 input, however, under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB, the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
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ClockWorksTM SY10E196 SY100E196
APPLICATIONS INFORMATION
Analog Input Charateristics: Ftune = VCC to VEE
140 120
Propagation Delay (ps)
100 80 60 40 20 0 -4.5
-3.5
-2.5 Ftune Voltage (V)
-1.5
-0.5
Propagation Delay vs Ftune Voltage (100E196)
100 90 80
Propagation Delay (ps)
70 60 50 40 30 20 10 0 -5 -4 -3 -2 -1 -0
Ftune Voltage (V)
Propagation Delay vs Ftune Voltage (10E196)
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ClockWorksTM SY10E196 SY100E196
To Select Multiplexers
Bit 0 D0 Q0 D3 LEN Reset Set LEN Reset Set Reset LEN LEN Reset Reset SET MIN SET MAX D1 Q1 D2 Q2
Bit 1
Bit 2
Bit 3 Q3 D4 LEN Reset Set
Bit 4 Q4 D5 LEN Reset Set
Bit 5 Q5 D6 LEN Reset Set
Bit 6 Q6
Bit 7
CASCADE
D7
Q7
CASCADE
LEN Reset
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Figure 2. Expansion of the Latch Section of the E196 Block Diagram
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ClockWorksTM SY10E196 SY100E196
Using the FTUNE Analog Input The analog FTUNE pin on the E196 device is intended to enhance the 20ps resolution capabilities of the fully digital E195. The level of resolution obtained is dependent on the number of increments applied to the appropriate range on the FTUNE pin. To provide another level of resolution, the FTUNE pin must be capable of adjusting the delay by greater than the 20ps digital resolution. As shown in the provided graphs, this requirement is easily achieved since a 100ps delay can be achieved over the entire FTUNE voltage range.This extra analog range ensures that the FTUNE pin will be capable, even under worst case conditions, of covering the digital resolution. Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. To determine the voltage range necessary for the FTUNE input, the graphs provided should be used. As an example, if a range of 40ps is selected to cover worst case conditions and ensure coverage of the digital range, from the 100E196 graph a voltage range of -3.25V to -4V would be necessary on the FTUNE pin. Obviously, there are numerous voltage ranges which can be used to cover a given delay range. Users are given the flexibility to determine which one best fits their design.
ADDRESS BUS (A0 - A6) A7
LINEAR INPUT
D6
D2
D4
D5
D3
D4
D7
D2
D1 D0 LEN VEE Input IN E196 Chip #1
D3
FTUNE VCC VCCO Q Q VCCO
D1 D0 LEN VEE IN E196 Chip #2
D5
D6
D7
FTUNE VCC VCCO Q Output Q VCCO
CASCADE
CASCADE
VBB
VBB
Figure 1. Cascading Interconnect Architecture
Cascading Multiple E196s To increase the programmable range of the E196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple E196s without the need for any external gating. Furthermore, this capability requires only one more address line per added E196. Obviously, cascading multiple PDCs will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay. Figure 1 illustrates the interconnect scheme for cascading two E196s. As can be seen, this scheme can easily be expanded for larger E196 chains. The D7 input of the E196 is the cascade control pin. With the interconnect scheme of Figure 1, when D7 is asserted, it signals the need for a larger programmable range than is achievable with a single device.
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An expansion of the latch section of the block diagram is pictured below. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D7 of chip #1 above is low, the cascade output will also be low, while the cascade bar output will be a logical high. In this condition, the SET MIN pin of chip #2 will be asserted and, thus, all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Since the RESET and SET inputs of the latches are overriding, any changes on the A0-A6 address bus will not affect the operation of chip #2. Chip #1, on the other hand, will have both SET MIN and SET MAX de-asserted so that its delay will be controlled entirely by the address bus A0-A6. If the delay needed is greater than can be achieved with 31.75 gate
CASCADE
EN
SET MAX
EN
SET MIN
CASCADE
SET MIN
SET MAX
IN
IN
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ClockWorksTM SY10E196 SY100E196
delays (1111111 on the A0-A6 address bus), D7 will be asserted to signal the need to cascade the delay to the next E196 device. When D7 is asserted, the SET MIN pin of chip #2 will be de-asserted and the delay will be controlled by the A0-A6 address bus. Chip #1, on the other hand, will have its SET MAX pin asserted, resulting in the device delay to be independent of the A0-A6 address bus. When the SET MAX pin of chip #1 is asserted, the D0 and D1 latches will be reset, while the rest of the latches will be set. In addition, to maintain monotonicity, an additional gate delay is selected in the cascade circuitry. As a result, when D7 of chip #1 is asserted, the delay increases from 31.75 gates to 32 gates. A 32-gate delay is the maximum delay setting for the E196. When cascading multiple PDCs, it will prove more costeffective to use a single E196 for the MSB of the chain, while using E195 for the lower order bits. This is due to the fact that only one fine tune input is needed to further reduce the delay step resolution.
PRODUCT ORDERING CODE
Ordering Code SY10E196JC SY10E196JCTR SY100E196JC SY100E196JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
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ClockWorksTM SY10E196 SY100E196
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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